Trying to get the sleep / reset cycle working in u-boot (look for a subsequent post) I managed to generate some dodgy assembler and the next thing you know...
Luckily I had a nice JTAG adapter lyining around, an Olimex ARM-USB-OCD. The soldering wasn't too tricky, but here is a detailed picture to help out the weary:
The interesting part was getting OpenOCD to play along nicely. To get OpenOCD working you need some configuration scripts that identify your CPU, JTAG adapter etc.
Here is the Z2 specific script (save this as e.g. z2.cfg):
And the ARM-USB-OCD configuration (save this as e.g. arm-usb-ocd.cfg):# config for ZipitZ2
jtag newtap pxa270 cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id 0x49265013 -expected-id 0x79265013
target create pxa270.cpu xscale -endian little -chain-position pxa270.cpu -variant pxa27x
# maps to PXA internal RAM.
pxa270.cpu configure -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
flash bank pxa270.flash cfi 0x00000000 0x1000000 2 2 pxa270.cpu
# Olimex ARM-USB-OCD
ft2232_device_desc "Olimex OpenOCD JTAG"
ft2232_vid_pid 0x15BA 0x0003
reset_config trst_and_srst separate
What is interesting to note in the script above are the jtag_nsrst_delay and jtag_ntrst_delay values. The ARM-USB-OCD has separate lines for SRST and TSRT and the above values were required to get reset halt to work reliably in OpenOCD.
Reflashing u-boot brought the Z2 back to life and I now have a JTAG debug option. I should have done this years ago!
edit: stupidly I forgot to thank the original JTAG legend GPSFan for his help and pictures and G1PowerMac for his site.